Senior Staff VLSI Design Engineer (SystemC, Functional Modeling, C++ , Verification)

Job Description Job responsibilities: - Hands-on contributions coding C++ & System C models & test creation - Debug issues in Firmware environment - Validating the developed model using systemC/SV/UVM testbench - Debug failures and root-cause it by interacting with other teams/groups Etc. - The candidate will also have to mentor junior engineers