STA signoff

- Lead block-level and full-chip STA signoff for HBM products across all PVT corners. - Own development and validation of SDC constraints , including clocks, generated clocks, false paths, multicycle paths, case analysis, and async constraints. - Drive timing closure by analyzing and resolving setup/hold, recovery/removal, slew, fanout, and clock-related violations. - Implement clocking solutions for complex HBM designs, including generated clocks, pulse clocks, and zero-cycle, single-cycle, and multi-cycle timing paths. - Correlate STA results with simulation to improve signoff accuracy. - Drive automation and productivity improvements using Tcl/Python for timing analysis, reporting, constraint generation, and debug workflows. - Collaborate closely with Design, Verification, Layout teams to achieve successful tapeout and product qualification. - Mentor engineers and provide technical leadership in STA methodology, timing closure, and signoff best practices. - Capable of Characterizing Basic Standard Cells - Lead technical reviews, risk assessments, and signoff readiness discussions for next-generation HBM products. - Strong experience in STA signoff using PrimeTime or equivalent tools. - Deep understanding of HBM/DRAM architectures and memory timing concepts. - Expertise in SDC development, clock modeling, OCV/AOCV/POCV, and timing closure. - Strong Tcl/Python scripting and automation skills. - Experience with full-chip timing signoff for complex SoC or memory products. - Proven record of technical leadership, innovation, and mentoring. - . Required Qualifications - Education Qualification : BE or MTECH with 5+ Years of experience - Minimum 6+ yrs of hands-on experience in STA signoff. - strong communication skills - Cross site & cross geo interaction Qualifications: B.Tech/MTech Skills: Sta Experience: 6.00-12.00 Years