Staff Engineer, VLSI Design Engineering (UVM, System Verilog) with 8 to 12 years of experience

Job Description Job responsibilities: - Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs - Design and implement verification environments using industry-standard UVM (Universal Verification Methodology) frameworks - Develop reusable and scalable verification components, including bus functional models, monitors, checkers, and scoreboards - Drive functional coverage-driven verification closure and ensure comprehensive design validation including Functional Coverage planning, development, debug and closure - Develop and maintain System Verilog Assertions (SVA) for design verification, including coding, porting, and maintenance activities - Collaborate with design architects, RTL designers, and post-silicon validation teams to ensure seamless verification integration - Create and optimize verification automation tools and scripts to enhance design and verification productivity - Investigate, debug, and perform root-cause analysis of design failures through cross-functional team collaboration - Mentor junior engineers and contribute to the continuous improvement of verification methodologies and best practices